PrimeCell ® SingleMaster DMA Controller (PL081) Technical Reference Manual

Revision: r1p2


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the SMDMAC
1.1.1. Features of the SMDMAC
1.2. Product revisions
2. Functional Overview
2.1. SMDMAC functional description
2.1.1. AHB slave interface
2.1.2. Control logic and register bank
2.1.3. DMA request and response interface
2.1.4. Channel logic and channel register bank
2.1.5. Interrupt request
2.1.6. AHB master interface
2.1.7. Channel hardware
2.1.8. Test registers
2.1.9. DMA request priority
2.2. System considerations
2.3. System connectivity
2.3.1. AHB interface
2.3.2. AHB slave interface
2.3.3. AHB master interface
2.3.4. Interrupt generation logic
2.3.5. Interrupt controller connectivity
2.3.6. DMA request and response connectivity
2.4. Use with memory management unit basedsystems
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. Register fields
3.2. Programming the SMDMAC
3.2.1. Enabling the SMDMAC
3.2.2. Disabling the SMDMAC
3.2.3. Enabling a DMA channel
3.2.4. Disabling a DMA channel
3.2.5. Set up a new DMA transfer
3.2.6. Halting a DMA channel
3.2.7. Programming a DMA channel
3.3. Summary of SMDMAC registers
3.4. Register descriptions
3.4.1. Interrupt Status Register
3.4.2. Interrupt Terminal Count Status Register
3.4.3. Interrupt Terminal Count Clear Register
3.4.4. Interrupt Error Status Register
3.4.5. Interrupt Error Clear Register
3.4.6. Raw Interrupt Terminal Count StatusRegister
3.4.7. Raw Error Interrupt Status Register
3.4.8. Enabled Channel Register
3.4.9. Software Burst Request Register
3.4.10. Software Single RequestRegister
3.4.11. Software Last Burst Request Register
3.4.12. Software Last Single Request Register
3.4.13. Configuration Register
3.4.14. Synchronization Register
3.4.15. Channel registers
3.4.16. Peripheral Identification Registers
3.4.17. PrimeCell Identification Registers
3.5. Address generation
3.6. Scatter/gather
3.6.1. Linked list items
3.6.2. Programming the SMDMAC for scatter/gather DMA
3.7. Interrupt requests
3.7.1. Combined terminal count and error interrupt sequenceflow
3.7.2. Terminal count interrupt sequence flow
3.7.3. Error interrupt sequence flow
3.7.4. Interrupt polling sequence flow
3.8. SMDMAC data flow
3.8.1. Peripheral-to-memory, or memory-to-peripheralDMA flow
3.8.2. Peripheral-to-peripheralDMA flow
3.8.3. Memory-to-memory DMA flow
4. Programmer’s Model for Test
4.1. SMDMAC test harness overview
4.2. Scan testing
4.3. Test register descriptions
4.3.1. Test Control Register
4.3.2. Integration Test OutputRegister 1
4.3.3. Integration Test Output Register 2
4.3.4. Integration Test Output Register 3
4.4. Integration test
4.4.1. Input signals
4.4.2. Output signals
A. Signal Descriptions
A.1. DMA interrupt request signals
A.2. DMA request and response signals
A.3. AHB slave signals
A.4. AHB master signals
A.5. AHB master bus request signals
A.6. Scan test control signals
B. DMA Interface
B.1. DMA request signals
B.2. DMA response signals
B.3. Flow control
B.4. Transfer types
B.4.1. Peripheral-to-memorytransaction under SMDMAC flow control
B.4.2. Memory-to-peripheral transaction underSMDMAC flow control
B.4.3. Memory-to-memory transaction underSMDMAC flow control
B.4.4. Peripheral-to-peripheral transferunder SMDMAC flow control
B.4.5. Memory-to-peripheraltransaction under peripheral flow control
B.4.6. Peripheral-to-memorytransactions under peripheral flow control
B.4.7. Peripheral-to-peripheraltransactions under source peripheral flow control
B.4.8. Peripheral-to-peripheral transactions under destinationperipheral flow control
B.5. Signal timing
B.6. Functional timing diagram
B.7. SMDMAC transfer timing diagram
C. Scatter/Gather
C.1. Scatter/gather through linked listoperation
Glossary

List of Figures

1. Key to timing diagram conventions
2.1. SMDMAC block diagram
2.2. AHB master
2.3. SMDMAC connectivity
2.4. Connection for higher performancesystems
2.5. Connection for lower performancesystems
2.6. Complex example of connectivity
2.7. Simple example of connectivity
3.1. DMACIntStatus Register bit assignments
3.2. DMACIntTCStatus Register bit assignments
3.3. DMACIntTCClear Register bit assignments
3.4. DMACIntErrorStatus Register bit assignments
3.5. DMACIntErrClr Register bit assignments
3.6. DMACRawIntTCStatus Register bit assignments
3.7. DMACRawIntErrorStatus Register bitassignments
3.8. DMACEnbldChns Register bit assignments
3.9. DMACSoftBReq Register bit assignments
3.10. DMACSoftSReq Register bit assignments
3.11. DMACSoftLBReq Register bit assignments
3.12. DMACSoftLSReq Register bit assignments
3.13. DMACConfiguration Register bit assignments
3.14. DMACSync Register bit assignments
3.15. DMACCxLLI Register bit assignments
3.16. DMACCxControl Register bit assignments
3.17. DMACCxConfiguration Register bitassignments
3.18. Peripheral Identification Registerbit assignments
3.19. DMACPeriphID0 Register bit assignments
3.20. DMACPeriphID1 Register bit assignments
3.21. DMACPeriphID2 Register bit assignments
3.22. DMACPeriphID3 Register bit assignments
3.23. PrimeCell Identification Register bitassignments
3.24. DMACPCellID0 Register bit assignments
3.25. DMACPCellID1 Register bit assignments
3.26. DMACPCellID2 Register bit assignments
3.27. DMACPCellID3 Register bit assignments
4.1. DMACITCR Register bit assignments
4.2. DMACITOP1 Register bit assignments
4.3. DMACITOP2 Register bit assignments
4.4. DMACITOP3 Register bit assignments
B.1. Peripheral-to-memory transactioncomprising bursts
B.2. Peripheral-to-memory transactioncomprising single requests
B.3. Peripheral-to-memory transactioncomprising bursts and single requests
B.4. Memory-to-peripheral transactioncomprising bursts
B.5. Memory-to-peripheral transactioncomprising single requests
B.6. Memory-to-peripheral transactioncomprising bursts that are not multiples of the burst size
B.7. Memory-to-memory transaction underDMA flow control
B.8. Peripheral-to-peripheral transactioncomprising bursts
B.9. Peripheral-to-peripheral transactioncomprising single transfers
B.10. Peripheral-to-peripheral transactioncomprising bursts and single requests
B.11. Memory-to-peripheral transactionunder peripheral flow control comprising bursts
B.12. Memory-to-peripheral transactionunder peripheral flow control comprising single transfers
B.13. Memory-to-peripheral transactionunder peripheral flow control comprising bursts and single transfers
B.14. Peripheral-to-memory transactionunder peripheral flow control comprising bursts
B.15. Peripheral-to-memory transactionunder peripheral flow control comprising single transfers
B.16. Peripheral-to-memory transactionunder peripheral flow control comprising bursts and single transfers
B.17. Peripheral-to-peripheral transactionunder source peripheral flow control comprising bursts
B.18. Peripheral-to-peripheral transactionunder source peripheral flow control comprising single transfers
B.19. Peripheral-to-peripheral transactionunder source peripheral flow control comprising bursts and singletransfers
B.20. Peripheral-to-peripheral transactionunder destination peripheral flow control comprising bursts
B.21. Peripheral-to-peripheral transactionunder destination peripheral flow control comprising single transfers
B.22. Peripheral-to-peripheral transactionunder destination peripheral flow control comprising bursts andsingle transfers
B.23. DMA interface timing
B.24. SMDMAC transfer timing diagram
C.1. LLI example

List of Tables

2.1. Endian behavior
3.1. Register summary
3.2. DMACIntStatus Register bit assignments
3.3. DMACIntTCStatus Register bit assignments
3.4. DMACIntTCClear Register bit assignments
3.5. DMACIntErrorStatus Register bit assignments
3.6. DMACIntErrClr Register bit assignments
3.7. DMACRawIntTCStatus Register bit assignments
3.8. DMACRawIntErrorStatus Register bit assignments
3.9. DMACEnbldChns Register bit assignments
3.10. DMACSoftBReq Register bit assignments
3.11. DMACSoftSReq Register bit assignments
3.12. DMACSoftLBReq Register bit assignments
3.13. DMACSoftLSReq Register bit assignments
3.14. DMACConfiguration Register bit assignments
3.15. DMACSync Register bit assignments
3.16. DMACCxSrcAddr Registers bit assignments
3.17. DMACCxDestAddr Register bit assignments
3.18. DMACCxLLI Register bit assignments
3.19. DMACCxControl Register bit assignments
3.20. Source or destination burst size
3.21. Source or destination transfer width
3.22. Protection bits
3.23. DMACCxConfiguration Register bit assignments
3.24. Flow control and transfer type bits
3.25. DMACPeriphID0 Register bit assignments
3.26. DMACPeriphID1 Register bit assignments
3.27. DMACPeriphID2 Register bit assignments
3.28. DMACPeriphID3 Register bit assignments
3.29. DMACPCellID0 Register bit assignments
3.30. DMACPCellID1 Register bit assignments
3.31. DMACPCellID2 Register bit assignments
3.32. DMACPCellID3 Register bit assignments
4.1. DMACITCR Register bit assignments
4.2. DMACITOP1 Register bit assignments
4.3. DMACITOP2 Register bit assignments
4.4. DMACITOP3 Register bit assignments
A.1. DMA interrupt request signal descriptions
A.2. DMA request and response signal descriptions
A.3. AHB slave signal descriptions
A.4. AHB master signal descriptions
A.5. AHB master bus request signal descriptions
A.6. Internal scan test control signal descriptions
B.1. DMA request signal usage

Proprietary Notice

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A May2001 First release.
Revision B July2001 Section 3.8.1 and 3.8.2 revised. Figure B-9and B-17 revised.Section added: Memory-to-peripheral transactionunder DMA Controller flow control.
Revision C February2003 Release for revision r1p1.
Revision D 28January 2004 First Issue for r1p2. Incorporatingerrata from Issue C.
Revision E 20 December2005 Second Issue for r1p2. Addressing defectsand general maintenance.
Copyright © 2001, 2003-2005 ARM Limited. All rights reserved. ARM DDI 0218E
Non-Confidential