3.8.3. DMAS[1:0]

The DMAS[1:0] bus encodes the size of the transfer. The ARM9EJ‑S core can transfer word, halfword, and byte quantities. This is encoded on DMAS[1:0] as shown in Table 3.6.

Table 3.6. Transfer widths

DMAS[1:0]

Transfer width

00

Byte

01

Halfword

10

Word

11

Reserved

The size of transfer does not change during a burst of S cycles. Bursts of halfword or byte accesses are not possible on the ARM9EJ-S core data interface.

Note

A writable memory system for the ARM9EJ‑S core must have individual byte write enables. Both the ARM C compiler and the debug tool chain (for example, Multi-ICE) assume that arbitrary bytes in the memory can be written. If individual byte write capability is not provided, you might not be able to use these tools.

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