3.6. Instruction interface cycle types

The ARM9EJ‑S instruction interface is pipelined. The address class signals and the memory request signals are broadcast in the bus cycle ahead of the bus cycle to which they refer. This gives the maximum time for a memory cycle to decode the address, and respond to the access request.

A single memory cycle is shown in Figure 3.1.

Figure 3.1. Simple memory cycle

The ARM9EJ‑S core instruction interface can perform three different types of memory cycle. These are indicated by the state of the InMREQ and ISEQ signals. Memory cycle types are encoded on the InMREQ and ISEQ signals as shown in Table 3.4.

Table 3.4. Cycle types

InMREQ

ISEQ

Cycle type

Description

0

0

N cycle

Nonsequential cycle

0

1

S cycle

Sequential cycle

1

X

I cycle

Internal cycle

A memory controller for the ARM9EJ‑S core must commit to an instruction memory access only on an N cycle or an S cycle.

The ARM9EJ‑S instruction interface has three types of memory cycle:

Nonsequential cycle

During this the ARM9EJ‑S core requests a transfer to or from an address that is unrelated to the address used in the preceding cycle. See Instruction interface, Nonsequential cycles.

Sequential cycle

During this the ARM9EJ‑S core requests a transfer to or from an address that is either one word, or one halfword greater than the address used in the preceding Sequential or Nonsequential cycle. See Instruction interface, Sequential cycles.

Internal cycle

During this the ARM9EJ‑S core does not require a transfer because it is performing an internal function, and no useful prefetching can be performed at the same time.

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