3.6.1. Instruction interface, Nonsequential cycles

A Nonsequential instruction Fetch is the simplest form of an ARM9EJ‑S instruction interface cycle, and occurs when the ARM9EJ‑S core requests a transfer from an address that is unrelated to the address used in the preceding cycle. The memory controller must initiate a memory access to satisfy this request.

The address class signals and the InMREQ, ISEQ = N cycle signals are broadcast on the instruction interface bus. At the end of the next bus cycle the instruction is transferred to the CPU from memory. This is shown in Figure 3.2.

Figure 3.2. Nonsequential instruction Fetch cycle

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