3.6.4. Canceled memory cycles

If IKILL is asserted, then the instruction request made (with InMREQ and ISEQ) in the previous cycle must be abandoned and must not make any programmer-visible persistent changes of state to the system.

The signal IKILL is only ever asserted if an instruction request is made in the previous clock cycle. It must be used to condition both InMREQ and ISEQ. IKILL only changes after the rising edge of CLK when CLKEN was asserted.

Figure 3.4. Completed instruction Fetch

An example of an instruction Fetch that is not canceled by IKILL is shown in Figure 3.4, an example of an instruction Fetch canceled by IKILL is shown in Figure 3.5.

Figure 3.5. Instruction Fetch canceled by IKILL

A memory system controller must ensure that an instruction request that is revoked using IKILL must not initiate a request on the AHB (or other system bus). A lookup can be performed in a Level 1 cache or TLB, but no linefill or page table walk must result from an access that has been canceled with IKILL.

The memory system controller is also responsible for ensuring that no programmer visible state updates occur.

A canceled instruction Fetch by IKILL is followed by one of:

Figure 3.6. Canceled instruction Fetch followed by a Sequential access

Figure 3.9 illustrates two Sequential Fetches to the same address that are both canceled.

Figure 3.7. Canceled instruction fetch followed by an internal cycle

Figure 3.8. Canceled instruction Fetch followed by a Nonsequential fetch

Figure 3.9. Two canceled Sequential instruction fetches

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