B.10. EmbeddedICE-RT logic

The EmbeddedICE-RT logic is integral to the ARM9EJ-S core. It has two hardware breakpoint or watchpoint units, each of which can be configured to monitor either the instruction memory interface or the data memory interface. Each watchpoint unit has registers that set the address, data, and control fields for both values and masks. The registers used are shown in Table B.5.

Because the ARM9EJ-S core has a Harvard Architecture, you must specify if the watchpoint unit examines the instruction or the data interface. This is specified by bit 3 of the control value register:

There cannot be a don’t care case for bit 3 because the comparators cannot compare the values on both buses simultaneously. Therefore, bit 3 of the control mask register is always clear and cannot be programmed HIGH. Bit 3 also determines if the internal IBREAKPT or DWPT signal must be driven by the result of the comparison. Figure B.6 gives an overview of the operation of the EmbeddedICE-RT logic.

The general arrangement of the EmbeddedICE-RT logic is shown in Figure B.6.

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