4.2.3. Re-enabling interrupts after an interrupt exception

You must take care when re-enabling interrupts (for example at the end of an interrupt routine or with a reentrant interrupt handler). You must ensure that the original source of the interrupt has been removed before interrupts are enabled again on the ARM9EJ-S core. If you cannot guarantee this, the ARM9EJ-S core might retake the interrupt exception prematurely. When considering the timing relation of removing the source of interrupt and re-enabling interrupts on the ARM9EJ-S core, you must take into account the pipelined nature of the ARM9EJ-S core and the memory system to which it is connected. For example, the instruction that causes the removal of the interrupt request (that is, de-assertion of nFIQ or nIRQ) typically does not take effect until after the Memory stage of that instruction. The instruction that re-enables interrupts on the ARM9EJ-S core can cause the ARM9EJ-S core to be sensitive to interrupts as early as the Execute stage of that instruction.For example, consider the following instruction sequence:

STR r0, [r1] ;Write to interrupt controller, clearing interruptSUBS pc, r14, #4 ;Return from interrupt routine

The execution of this code sequence is illustrated in Figure 4.1.

Figure 4.1. Retaking the FIQ exception

In Figure 4.1, the STR to the interrupt controller does not cause the de-assertion of the nFIQ input until cycle 4. The SUBS instruction causes the ARM9EJ-S core to be sensitive to interrupts during cycle 3.

Because of this timing relationship, the ARM9EJ-S core retakes the FIQ exception in this example.The FIQDIS (and similarly IRQDIS) output from the ARM9EJ-S core indicates when the ARM9EJ-S core is sensitive to the state of the nFIQ (nIRQ) input (0 for sensitive, 1 for insensitive). If nFIQ is asserted in the same cycle that FIQDIS is LOW, the ARM9EJ-S core takes the FIQ exception in a later cycle, even if the nFIQ input is subsequently deasserted.There are several approaches that you can adopt to ensure that interrupts are not enabled too early on the ARM9EJ-S core. The best approach is highly dependent on the overall system, and can be a combination of hardware and software.

Example approaches are:

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