1.4.1. Extended ARM instruction set summary

The extended ARM instruction set summary is given in Table 1.2.

Table 1.2. ARM instruction set summary

MoveMoveMOV{cond}{S} Rd, <Oprnd2>
 Move NOTMVN{cond}{S} Rd, <Oprnd2>
 Move SPSR to registerMRS{cond} Rd, SPSR
 Move CPSR to registerMRS{cond} Rd, CPSR
 Move register to SPSRMSR{cond} SPSR{field}, Rm
 Move register to CPSRMSR{cond} CPSR{field}, Rm
 Move immediate to SPSR flagsMSR{cond} SPSR_flg, #32bit_Imm
 Move immediate to CPSR flagsMSR{cond} CPSR_flg, #32bit_Imm
ArithmeticAddADD{cond}{S} Rd, Rn, <Oprnd2>
 Add with carryADC{cond}{S} Rd, Rn, <Oprnd2>
 SubtractSUB{cond}{S} Rd, Rn, <Oprnd2>
 Subtract with carrySBC{cond}{S} Rd, Rn, <Oprnd2>
 Reverse subtractRSB{cond}{S} Rd, Rn, <Oprnd2>
 Reverse subtract with carryRSC{cond}{S} Rd, Rn, <Oprnd2>
 MultiplyMUL{cond}{S} Rd, Rm, Rs
 Multiply accumulateMLA{cond}{S} Rd, Rm, Rs, Rn
 Multiply unsigned longUMULL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply unsigned accumulate longUMLAL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply signed longSMULL{cond}{S} RdLo, RdHi, Rm, Rs
 Multiply signed accumulate longSMLAL{cond}{S} RdLo, RdHi, Rm, Rs
 CompareCMP{cond} Rd, <Oprnd2>
 Compare negativeCMN{cond} Rd, <Oprnd2>
 Saturating addQADD{cond} Rd, Rn, Rs
 Saturating add with doubleQDADD{cond} Rd, Rn, Rs
 Saturating subtractQSUB{cond} Rd, Rn, Rs
 Saturating subtract with doubleQDSUB{cond} Rd, Rn, Rs
 Multiply 16x16SMULxy{cond} Rd, Rm, Rs
 Multiply accumulate 16x16+32SMULAxy{cond} Rd, Rm, Rs, Rn
 Multiply 32x16SMULWx{cond} Rd, Rm, Rs
 Multiply accumulate 32x16+32SMLAWx{cond} Rd, Rm, Rs, Rn
 Multiply signed accumulate long 16x16+64SMLALx{cond} RdLo, RdHi, Rm, Rs
 Count leading zerosCLZ{cond} Rd, Rm
LogicalTestTST{cond} Rn, <Oprnd2>
 Test equivalenceTEQ{cond} Rn, <Oprnd2>
 ANDAND{cond}{S} Rd, Rn, <Oprnd2>
 XOREOR{cond}{S} Rd, Rn, <Oprnd2>
 ORORR{cond}{S} Rd, Rn, <Oprnd2>
 Bit clearBIC{cond}{S} Rd, Rn, <Oprnd2>
BranchBranchB{cond} label
 Branch with linkBL{cond} label
Branch and exchangeBX{cond} Rn
Branch, link and exchangeBLX{cond} label
Branch, link and exchangeBLX{cond} Rn
Branch and exchange to Jazelle stateBXJ{cond} Rm
LoadWordLDR{cond} Rd, <a_mode2>
 Word with User mode privilegeLDR{cond}T Rd, <a_mode2P>
 ByteLDR{cond}B Rd, <a_mode2>
 Byte with User mode privilegeLDR{cond}BT Rd, <a_mode2P>
 Byte signedLDR{cond}SB Rd, <a_mode3>
 HalfwordLDR{cond}H Rd, <a_mode3>
 Halfword signedLDR{cond}SH Rd, <a_mode3>
Multiple block data operationsStack operationsLDM{cond}<a_mode4L> Rd{!}, <reglist>
 Increment beforeLDM{cond}IB Rd{!}, <reglist>{^}
 Increment afterLDM{cond}IA Rd{!}, <reglist>{^}
 Decrement beforeLDM{cond}DB Rd{!}, <reglist>{^}
 Decrement afterLDM{cond}DA Rd{!}, <reglist>{^}
 Stack operations and restore CPSRLDM{cond}<a_mode4L> Rd{!}, <reglist+pc>^
 User registersLDM{cond}<a_mode4L> Rd{!}, <reglist>^
 Load doubleLDR{cond}D Rd, <a_mode3>
StoreWordSTR{cond} Rd, <a_mode2>
 Word with User mode privilegeSTR{cond}T Rd, <a_mode2P>
 ByteSTR{cond}B Rd, <a_mode2>
 Byte with User mode privilegeSTR{cond}BT Rd, <a_mode2P>
 HalfwordSTR{cond}H Rd, <a_mode3>
Multiple block data operationsStack operationsSTM{cond}<a_mode4S> Rd{!}, <reglist>
 Increment beforeSTM{cond}IB Rd{!}, <reglist>{^}
 Increment afterSTM{cond}IA Rd{!}, <reglist>{^}
 Decrement beforeSTM{cond}DB Rd{!}, <reglist>{^}
 Decrement afterSTM{cond}DA Rd{!}, <reglist>{^}
 User registersSTM{cond}<a_mode4S> Rd{!}, <reglist>^
 Store doubleSTR{cond}D Rd, <a_mode3>
Soft preloadMemory might prepare to load from addressPLD <a_mode2>
SwapWordSWP{cond} Rd, Rm, [Rn]
 ByteSWP{cond}B Rd, Rm, [Rn]
CoprocessorsData operationsCDP{cond} p<cpnum>, <op1>, CRd, CRn, CRm, <op2>
Move to ARM reg from coprocMRC{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move to coproc from ARM regMCR{cond} p<cpnum>, <op1>, Rd, CRn, CRm, <op2>
Move double to ARM reg from coprocMRRC{cond} p<cpnum>, <op1>, Rd, Rn, CRm
Move double to coproc from ARM regMCRR{cond} p<cpnum>, <op1>, Rd, Rn, CRm
LoadLDC{cond} p<cpnum>, CRd, <a_mode5>
StoreSTC{cond} p<cpnum>, CRd, <a_mode5>
Software interrupt SWI{cond} 24bit_Imm
Software breakpoint BKPT<immediate>

Addressing modes are summarized in Table 1.3.

Table 1.3. Addressing modes

Addressing mode 2Immediate offset[Rn, #+/-12bit_Offset]
 Register offset[Rn, +/-Rm]
 Scaled register offset[Rn, +/-Rm, LSL #5bit_shift_imm]
  [Rn, +/-Rm, LSR #5bit_shift_imm]
  [Rn, +/-Rm, ASR #5bit_shift_imm]
  [Rn, +/-Rm, ROR #5bit_shift_imm]
  [Rn, +/-Rm, RRX]
 Pre-indexed offset-
 Immediate[Rn, #+/-12bit_Offset]!
 Register[Rn, +/-Rm]!
 Scaled register[Rn, +/-Rm, LSL #5bit_shift_imm]!
  [Rn, +/-Rm, LSR #5bit_shift_imm]!
  [Rn, +/-Rm, ASR #5bit_shift_imm]!
  [Rn, +/-Rm, ROR #5bit_shift_imm]!
  [Rn, +/-Rm, RRX]!
 Post-indexed offset-
 Immediate [Rn], #+/-12bit_Offset
 Register [Rn], +/-Rm
 Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm
  [Rn], +/-Rm, LSR #5bit_shift_imm
  [Rn], +/-Rm, ASR #5bit_shift_imm
  [Rn], +/-Rm, ROR #5bit_shift_imm
  [Rn], +/-Rm, RRX
Addressing mode 2 (privileged)Immediate offset[Rn, #+/-12bit_Offset]
 Register offset[Rn, +/-Rm]
 Scaled register offset[Rn, +/-Rm, LSL #5bit_shift_imm]
  [Rn, +/-Rm, LSR #5bit_shift_imm]
  [Rn, +/-Rm, ASR #5bit_shift_imm]
  [Rn, +/-Rm, ROR #5bit_shift_imm]
  [Rn, +/-Rm, RRX]
 Post-indexed offset-
 Immediate [Rn], #+/-12bit_Offset
 Register [Rn], +/-Rm
 Scaled register [Rn], +/-Rm, LSL #5bit_shift_imm
  [Rn], +/-Rm, LSR #5bit_shift_imm
  [Rn], +/-Rm, ASR #5bit_shift_imm
  [Rn], +/-Rm, ROR #5bit_shift_imm
  [Rn], +/-Rm, RRX
Addressing mode 3Immediate offset[Rn, #+/-8bit_Offset]
  Pre-indexed [Rn, #+/-8bit_Offset]!
  Post-indexed [Rn], #+/-8bit_Offset
 Register offset[Rn, +/-Rm]
  Pre-indexed [Rn, +/-Rm]!
  Post-indexed [Rn], +/-Rm
Addressing mode 4 (load)IA Increment afterFD Full descending
 IB Increment beforeED Empty descending
 DA Decrement afterFA Full ascending
 DB Decrement beforeEA Empty ascending
Addressing mode 4 (store)IA Increment afterEA Empty ascending
 IB Increment beforeFA Full ascending
 DA Decrement afterED Empty descending
 DB Decrement beforeFD Full descending
Addressing mode 5 (load)Immediate offset[Rn, #+/-(8bit_Offset*4)]
  Pre-indexed[Rn, #+/-(8bit_Offset*4)]!
  Post-indexed[Rn], #+/-(8bit_Offset*4)

Oprnd2 is summarized in Table 1.4.

Table 1.4. Oprnd2

Immediate value#32bit_Imm
Logical shift leftRm LSL #5bit_Imm
Logical shift rightRm LSR #5bit_Imm
Arithmetic shift rightRm ASR #5bit_Imm
Rotate rightRm ROR #5bit_Imm
Logical shift leftRm LSL Rs
Logical shift rightRm LSR Rs
Arithmetic shift rightRm ASR Rs
Rotate rightRm ROR Rs
Rotate right extendedRm RRX

Fields are summarized in Table 1.5.

Table 1.5. Fields

_cControl field mask bit (bit 0)
_xExtension field mask bit (bit 1)
_sStatus field mask bit (bit 2)
_fFlags field mask bit (bit 3)

Condition fields are summarized in Table 1.6.

Table 1.6. Condition fields

NENot equal
HS/CSUnsigned higher or same
LO/CCUnsigned lower
PLPositive or zero
VCNo overflow
HIUnsigned higher
LSUnsigned lower or same
GEGreater or equal
LTLess than
GTGreater than
LELess than or equal
Copyright ©  2001, 2002. ARM Limited. All rights reserved.ARM DDI 0222B