1.4. ARM9EJ-S instruction set summary

This section provides:

A key to the ARM and Thumb instruction set tables is given in Table 1.1.

The ARM9EJ-S core is an implementation of the ARM architecture v5TE with ARM Jazelle technology. For a description of the ARM and Thumb instruction sets see the ARM Architecture Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.

Table 1.1. Key to instruction set tables

SymbolDescription
{cond}See Table 1.6.
<Oprnd2>See Table 1.4.
{field}See Table 1.5.
SSets condition codes (optional).
BByte operation (optional).
HHalfword operation (optional).
TForces DnTRANS to be active (0). Cannot be used with pre-indexed addresses.
<a_mode2>See Table 1.3.
<a_mode2P>See Table 1.3.
<a_mode3>See Table 1.3.
<a_mode4L>See Table 1.3.
<a_mode4S>See Table 1.3.
<a_mode5>See Table 1.3.
#32bit_ImmA 32‑bit constant, formed by right‑rotating an 8‑bit value by an even number of bits.
<reglist>A comma-separated list of registers, enclosed in braces ({and}).
xSelects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits. (T = top) B selects the LOW 16 bits. (B = bottom).
ySelects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits. (T = top) B selects the LOW 16 bits. (B = bottom).
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