8.1. Instruction cycle count summary

Table 8.1 shows the key to the other tables in this chapter.

Table 8.1. Key to tables

SymbolMeaning

b

The number of busy-wait states during coprocessor accesses.

n

The number of words transferred in an LDM/STM/LDC/STC.

C

Coprocessor register transfer cycle (C-cycle).

I

Internal cycle (I-cycle).

N

Nonsequential cycle (N-cycle).

S

Sequential cycle (S-cycle).

Table 8.2 summarizes the ARM9EJ-S instruction cycle counts and bus activity when executing the ARM instruction set.

Table 8.2. ARM instruction cycle counts

Instruction

Cycles

Instruction

bus

Data

bus

Comment

CLZ

1

1S

1I

All cases.

Data Op

1

1S

1I

Normal case, PC not destination.

Data Op

2

1S+1I

2I

With register controlled shift, PC not destination.

Data Op

3

2S+1N

3I

PC destination register, arithmetic data output (ADD, SUB, RSB, ADC, SBC).

Data Op

42S+1N+1I4I

PC destination register, logical data output (RSC, ORR, EOR, MOV, BIC).

Data Op

4

2S+1N+1I

4I

With operand shift, PC destination register.

LDR

1

1S

1N

Normal case, not loading PC.

LDR

2

1S+1I

1N+1I

Not loading PC and following instruction uses loaded word (1 cycle load-use interlock).

LDR

2

1S+1I

1N+1I

Not loading PC and shifted offset.

LDR

3

1S+2I

1N+2I

Not loading PC and shifted offset and following instruction uses loaded word (1 cycle load-use interlock).

LDR

3

1S+2I

1N+2I

Loaded byte, halfword, or unaligned word used by following instruction (2-cycle load-use interlock).

LDR

5

2S+2I+1N

1N+4I

PC is destination register.

LDR6

2S+3I+1N

1N+5I

PC is destination register, scaled register offset.

LDRD21S+1I1N+1SNormal case.
LDRD31S+2I1N+1S+1ILast loaded word used by following instruction.

STR

1

1S

1N

Normal case.

STR21S+1I1N+1IScaled offset.
STRD21S+1I1N+1SAll cases.

LDM

2

1S+1I

1S+1I

Loading 1 register, not the PC.

LDM

n

1S+(n-1)I

1N+(n-1)S

Loading n registers, n > 1, not loading the PC.

LDMn+11S+nI1N+(n-1)S+1ILoading n registers, n > 1, not loading the PC, last word loaded used by following instruction.

LDM

n+4

2S+1N+(n+1)I

1N+(n-1)S+4I

Loading n registers including the PC, n > 0.

LDM

5

2S+2I+1N

1N+4I

Load PC.

STM

2

1S+1I

1N+1I

Storing 1 register.

STM

n

1S+(n-1)I

1N+(n-1)S

Storing n registers, n > 1.

SWP

2

1S+1I

2N

Normal case.

SWP

3

1S+2I

2N+1I

Loaded word used by following instruction.

PLD11S1IAll cases, DnSPEC asserted.

B, BL, BX, BLX, BXJ

3

2S+1N

3I

All cases.

SWI, Undefined

3

2S+1N

3I

All cases.

Coprocessor absent

b+4

2S+1N+1I+bI

4I+bI

All cases.

CDP

b+1

1S+bI

(1+b)I

All cases.

LDC, STC

b+n

1S+(b+n-1)I

bI+1N+(n-1)S

All cases.

MCR

b+1

1S+bI

bI+1C

All cases.

MCRRb+21S+(b+1)IbI+2CAll cases.

MRC

b+1

1S+bI

bI+1C

Normal case.

MRC

b+2

1S+(b+1)I

(b+1)I+1C

Following instruction uses transferred data.

MRC (dest = PC)

b+4

1S+(b+3)I

(b+3)I+1C

Destination is PC.

MRRCb+21S+(b+1)IbI+2CNormal case.
MRRCb+31S+(b+2)I(b+1)I+2CFollowing instruction uses last transferred data.

MRS

2

1S+1I

2I

All cases.

MSR

1

1S

1I

If only flags are updated (mask_f).

MSR

3

1S+2I

3I

If any bits other than the flags are updated (all masks other than mask_f).

MUL, MLA

2

1S+1I

2I

Normal case.

MUL, MLA

3

1S+2I

3I

Following instruction uses the result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.

MULS, MLAS

4

1S+3I

4I

All cases, sets flags.

QADD, QDADD,

QSUB, QDSUB

1

1S

1I

Normal case.

QADD, QDADD,

QSUB, QDSUB

2

1S+1I

2I

Following instruction uses the result in its first Execute cycle.

SMULL, UMULL,

SMLAL, UMLAL

3

1S+2I

3I

Normal case.

SMULL, UMULL,

SMLAL, UMLAL

4

1S+3I

4I

Following instruction uses RdHi result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.

SMULLS, UMULLS,

SMLALS, UMLALS

5

1S+4I

5I

All cases, sets flags.

SMULxy, SMLAxy

1

1S

1I

Normal case.

SMULxy, SMLAxy

2

1S+1I

2I

Following instruction uses the result in its first Execute or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.

SMULWx, SMLAWx

1

1S

1I

Normal case.

SMULWx, SMLAWx

2

1S+1I

2I

Following instruction uses the result in its first Execute or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.

SMLALxy

2

1S+1I

2I

Normal case.

SMLALxy

3

1S+2I

3I

Following instruction uses RdHi result in its first Execute cycle or its first Memory cycle. Does not apply to a multiply accumulate using result for accumulate operand.

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