8.14. Load multiple registers

A load multiple (LDM) takes several cycles to execute, depending on the number of registers transferred and if the PC is in the list of registers transferred:

  1. During the first cycle, the ARM9EJ-S core calculates the address of the first word to be transferred, while performing an instruction Prefetch.

  2. During the second and subsequent cycles, ARM9EJ-S core reads the data requested in the previous cycle and calculates the address of the next word to be transferred. The new value for the base register is calculated.

When a Data Abort occurs, the instruction continues to completion. The ARM9EJ-S core prevents all register writing after the abort. The ARM9EJ-S core restores the modified base pointer (that the load activity before the abort occurred might have overwritten).

When the PC is in the list of registers to be loaded, the ARM9EJ-S core invalidates the current contents of the instruction pipeline. The PC is always the last register to be loaded, so an abort at any point prevents the PC from being overwritten.

Note

LDM with destination = PC cannot be executed in Thumb state. However, POP{Rlist, PC} equates to an LDM with destination = PC.

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