8.28. Coprocessor absent

If no coprocessor is able to process a coprocessor instruction, the instruction is treated as an UNDEFINED instruction. This enables software to emulate coprocessor instructions when no hardware coprocessor is present.

Note

By default, CHSD and CHSE must be driven to Absent unless the coprocessor instruction is being handled by a coprocessor. Coprocessor operations are only available in ARM state.

The cycle timings for coprocessor absent instructions are shown in Table 8.35.

Table 8.35. Coprocessor absent instruction cycle timing

Cycle

IA

IREQ[1]

INSTR

DA

DREQ[2]

RDATA/

WDATA

P[3]

LC[4]

CHSD

CHSE

Coprocessor

absent in

decode

Absent

1

pc+3i

I cycle

(pc+2i)

-

I cycle

1

0

-

-

2

0x4

N cycle

-

-

I cycle

-

0

0

-

-

3

0x8

S cycle

(0x4)

-

I cycle

-

0

0

-

4

0xC

S cycle

(0x8)

-

I cycle

-

0

0

-

(0xC)

-

Coprocessor

absent in

execute

Wait

1

pc+3i

I cycle

(pc+2i)

-

I cycle

1

0

Wait

.

pc+3i

I cycle

-

-

I cycle

-

0

0

Wait

n

pc+3i

I cycle

-

-

I cycle

-

0

0

Absent

n+1

0x4

N cycle

-

-

I cycle

-

0

0

-

n+2

0x8

S cycle

(0x4)

-

I cycle

-

0

0

n+3

0xC

S cycle

(0x8)

-

I cycle

-

0

0

(0xC)

-

[1] IREQ = InMREQ, ISEQ.

[2] DREQ = DnMREQ, DSEQ.

[3] P = PASS.

[4] LC = LATECANCEL.

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