5.5. Interlocked MCR

If the data for an MCR operation is not available inside the ARM9EJ-S pipeline during its first Decode cycle, the ARM9EJ-S pipeline interlocks for one or more cycles until the data is available. An example of this is where the register being transferred is the destination from a preceding LDR instruction. In this situation the MCR instruction enters the Decode stage of the coprocessor pipeline, and remains there until it can enter the Execute stage.


The CHSD must return its value in the second cycle (not interlocked).

Figure 5.5 gives an example of an interlocked MCR.

Figure 5.5. ARM9EJ-S core interlocked MCR

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