2.9.2. Entering an ARM exception

When handling an ARM exception the ARM9EJ‑S core:

  1. Preserves the address of the next instruction in the appropriate LR. When the exception entry is from:

    • ARM and Jazelle states, the ARM9EJ‑S copies the address of the next instruction into the LR (current PC + 4 or PC + 8 depending on the exception).

    • Thumb state, the ARM9EJ‑S writes the value of the PC into the LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return.

    The exception handler does not have to determine the state when entering an exception. For example, in the case of a SWI, MOVS PC, r14_svc always returns to the next instruction regardless of the state in which the SWI was executed (in ARM or Thumb state).

  2. Copies the CPSR into the appropriate SPSR.

  3. Forces the CPSR mode bits to a value that depends on the exception.

  4. Forces the PC to fetch the next instruction from the relevant exception vector.

The ARM9EJ‑S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.


Exceptions are always entered, handled, and exited in ARM state. When the processor is in Thumb state or Jazelle state and an exception occurs, the switch to ARM state takes place automatically when the exception vector address is loaded into the PC.

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