2.9.7. Aborts

An abort indicates that the current memory access cannot be completed. An abort is signaled by one of the two external abort input pins, IABORT and DABORT.

There are two types of abort:

IRQs are disabled when an abort occurs.

Prefetch Abort

This is signaled by an assertion on the IABORT input pin and checked at the end of each instruction Fetch.

When a Prefetch Abort occurs, the ARM9EJ‑S core marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place.

After dealing with the cause of the abort, the handler executes the following instruction irrespective of the processor operating state:

SUBS PC,R14_abt,#4

This action restores both the PC and the CPSR, and retries the aborted instruction.

Data Abort

This is signaled by an assertion on the DABORT input pin and checked at the end of each data access, both read and write.

The ARM9EJ-S core implements the base restored Data Abort model, that differs from the base updated Data Abort model implemented by the ARM7TDMI-S.

The difference in the Data Abort model affects only a very small section of operating system code, in the Data Abort handler. It does not affect user code.

With the base restored Data Abort model, when a Data Abort exception occurs during the execution of a memory access instruction, the base register is always restored by the processor hardware to the value it contained before the instruction was executed. This removes the requirement for the Data Abort handler to unwind any base register update, that might have been specified by the aborted instruction. This greatly simplifies the software Data Abort handler.

The abort mechanism enables you to implement a demand-paged virtual memory system. In such a system, the processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the requested data available, and retry the aborted instruction. The application program requires no knowledge of the amount of memory available to it, and its state is not affected by the abort.

After dealing with the cause of the abort, the handler must execute the following return instruction irrespective of the processor operating state at the point of entry:

SUBS PC,R14_abt,#8

This action restores both the PC and the CPSR, and retries the aborted instruction.

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