A.5. Coprocessor interface signals

The coprocessor interface signals are shown in Table A.5.

Table A.5. Coprocessor interface signals

Name

Direction

Description

PASS

Output

This signal indicates that there is a coprocessor instruction in the Execute stage of the pipeline, and it must be executed.

CHSD[1:0]

Coprocessor handshake decode

Input

The handshake signals from the Decode stage of the pipeline follower of the coprocessor.

CHSE[1:0]

Coprocessor handshake execute

Input

The handshake signals from the Execute stage of the pipeline follower of the coprocessor.

LATECANCEL

Coprocessor late cancel

Output

If HIGH during the first memory cycle of a coprocessor instruction, then the coprocessor must cancel the instruction without changing any internal state. This signal is only asserted in cycles where the previous instruction accessed memory and a Data Abort occurred.

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