B.10.5. Debug control register

The debug control register is 6 bits wide. Writing control bits occurs during a register write access (with the read/write bit HIGH). Reading control bits occurs during a register read access (with the read/write bit LOW).

Figure B.9 shows the function of each bit in this register.

Figure B.9. Debug control register format

These functions are described in Table B.8 and Table B.9.

Table B.8. Debug control register bit functions





[5]Embedded-ICE disableControls the address and data comparison logic contained within the Embedded-ICE logic. When set to 1, the address and data comparators are disabled. When set to 0, the address and data comparators are enabled. You can use this bit to save power in a system where the Embedded-ICE functionality is not required. The reset state of this bit is 0 (comparators enabled). An extra piece of logic initialized by debug reset ensures that the Embedded-ICE logic is automatically disabled out of reset. This extra logic is set by debug reset and is automatically reset on the first access to scan chain 2.


Monitor mode enable

Controls the selection between monitor mode debug (monitor mode enable = 1) and Halt mode debug. In monitor mode, breakpoints and watchpoints cause Prefetch Aborts and Data Aborts to be taken (respectively). At reset, the monitor mode enable bit is set to 1.


Reservedmust be zero.



If bit 2 (INTDIS) is asserted, the interrupt signals to the processor are inhibited. Table C‑8 shows interrupt signal control.




These bits enable the values on DBGRQ and DBGACK to be forced.

Table B.9. Interrupt signal control













Both IRQ and FIQ are disabled when the processor is in debug state (DBGACK =1), or when INTDIS is forced.

As shown in Figure B.11, the value stored in bit 1 of the control register is synchronized and then ORed with the external EDBGRQ before being applied to the processor.

In the case of DBGACK, the value of DBGACK from the core is ORed with the value held in bit 0 to generate the external value of DBGACK seen at the periphery of the ARM9EJ-S core. This enables the debug system to signal to the rest of the system that the core is still being debugged even when system-speed accesses are being performed (in which case the internal DBGACK signal from the core is LOW).

The structure of the debug control and status registers is shown in Figure B.11.

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