B.1.2. TAP state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. Figure B.2 shows the state transitions that occur in the TAP controller. The state numbers shown in the diagram are output from the ARM9EJ-S core on the DBGTAPSM[3:0] bits.

Figure B.2. Test access port controller state transitions[1]



[1] From IEEE Std 1149.1-1990. Copyright 1999 IEEE. All rights reserved.

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