7.2.1. Full system reset

You must apply full system reset to the ARM9EJ-S core when power is first applied to the system. In this case, the leading (falling) edge of the reset signals (nRESET and DBGnTRST) do not have to be synchronous to CLK. The trailing (rising) edge of the reset signals must be set up and held about the rising edge of the clock. You must do this to ensure that the entire system leaves reset in a predictable manner. This is particularly important in multi-processor systems. Figure 7.1 shows the application of system reset.

Figure 7.1. System reset

It is recommended that you assert the reset signals for at least three CLK cycles to ensure correct reset behavior. Adopting a three-cycle reset eases the integration of other ARM parts into the system, for example, ARM9TDMI-based designs.

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