ARM9EJ-S Technical Reference ManualRevision: r1p2
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8.18.1. Interlocks

A swap operation can cause one and two-cycle interlocks in a similar fashion to a load register instruction.

Table 8.25 shows the cycle timing for the basic data swap operation.

Table 8.25. Data swap cycle timing

Cycle

IA

InMREQ,

ISEQ

INSTR

DA

DnMREQ,

DSEQ

RDATA

WDATA

Normal

1

pc+3i

I cycle

(pc+2i)

da

N cycle

2

pc+3i

S cycle

-

da

N cycle

(da)

-

(pc+3i)

-

Rd

1 cycle interlock

1

pc+3i

I cycle

(pc+2i)

da

N cycle

2

pc+3i

I cycle

-

da

N cycle

(da)

-

3

pc+3i

S cycle

-

-

I cycle

-

Rd

(pc+3i)

-

-

2 cycle interlock

1

pc+3i

I cycle

(pc+2i)

da

N cycle

2

pc+3i

I cycle

-

da

N cycle

(da)

-

3

pc+3i

I cycle

-

-

I cycle

-

Rd

4

pc+3i

S cycle

-

-

I cycle

-

-

(pc+3i)

-

-

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