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The update block is used to calculate the update value of the RTC. The update block also generates an equivalent match value to be compared with the counter value in the CLK1HZ domain. It asserts an interrupt when the two values are equal.
There is a distinction between the RTC value and counter value:
An update value (through the RTCLR register) is applied to the counter value in the update block. The resulting offset is applied to the current counter value to generate an updated RTC value.
Reads from the data register (RTCDR) return the current value of the RTC alone and not that of the counter, as they are different.
Generally, an update to the absolute RTC value occurs after two rising clock edges of PCLK.
Also, an RTC enable bit is set when 1 is written to bit[0] of the RTC control register. When set, the RTC is started and subsequent writes have no effect. A read of bit[0] indicates the status of the RTC enable signal.
The Offset register is zero on reset. It clocks through the offset value only when an update value is written to the RTC load register and holds that value until the next update is written.