4.3.1. Integration Test Control Register, RTCITCR

RTCITCR is the test control register. This general test register controls the operation of the RTC under test conditions. Table 4.2 shows the bit assignments for the RTCITCR register.

Table 4.2. RTCITCR register

BitsNameDescription
[31:3]-Reserved. Read as zero. Must be written as 0.
[2]TESTOFFSET

Test offset enable. When this bit is set to 1, data can be written to and read from the offset register for test purposes.

When this bit is set to 0, data cannot be written to or read from the offset register (normal operation). The reset value is 0.

[1]TESTCOUNT

Test count enable. When this bit is set to 1, data can be written to and read from the counter register for test purposes.

When this bit is set to 0, data cannot be written to or read from the counter register (normal operation). The reset value is 0.

[0]ITENIntegration test enable. When this bit is 1, the RTC is placed in integration test mode, otherwise it is in normal mode.

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