4.3. Test registers

The RTC test registers are memory-mapped as shown in Table 4.1.

Table 4.1. Test registers memory map

AddressTypeWidthReset valueDescription
0x080RW30x00000000Integration Test Control Register, RTCITCR
0x084RW00x00000000Integration Test Input register, RTCITIP
0x088RW10x00000000Integration Test Output register, RTCITOP
0x08CRW320x00000000Test Offset register, RTCTOFFSET
0x090RW320x00000000Test Count register, RTCTCOUNT


Test registers must not be accessed during normal operation.

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