2.2.6. Counter block

The counter is a free-running 32-bit counter that increments by one on each rising CLK1HZ edge. The counter wraps from 0xFFFFFFFF to 0x00000000 on overflow and continues incrementing. The counter is free-running and cannot be loaded directly. It counts up from 0x00000001 on reset.

A comparator is used to assert the RTCINTR interrupt when the current RTC value and match-compare register values are identical.

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