2.2.4. Update block

The update block is used to calculate the update value of the RTC. The update block also generates an equivalent match value to be compared with the counter value in the CLK1HZ domain.

There is a distinction between the RTC value and counter value:

Generally, an update to the absolute RTC value occurs after two rising clock edges of PCLK.

Also, an RTC enable bit is set when 1 is written to bit[0] of the Control Register. When set, the RTC is started but any subsequent write resets the current RTC value. A read of bit[0] indicates the status of the RTC enable signal. See Control Register, RTCCR.


The Offset register is zero on reset. It clocks through the offset value only when an update value is written to the Load Register and holds that value until the next update is written.

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