A.1. AMBA APB signals

The RTC is connected to the AMBA APB as a bus slave. Table A.1 describes the APB signals that are used and produced.

Table A.1. APB signal descriptions

Name

Type

Source or destination

Description

PCLK

Input

Clock generator

APB clock, used to time all bus transfers.

PRESETn

Input

Reset controller

Bus reset signal (active LOW).

PSEL

Input

APB bridge

When HIGH, this signal indicates that the RTC module has been selected by the AMBA APB bridge.

PENABLE

Input

APB bridge

APB enable signal.

PENABLE is asserted HIGH for one PCLK cycle, to enable a bus transfer cycle.

PWRITE

Input

APB bridge

When HIGH, this signal indicates a write to a peripheral and when LOW, a read from a peripheral.

This signal has the same timing as the peripheral address bus.

PADDR[11:2]

Input

APB bridge

Subset of AMBA APB address bus.

PWDATA[31:0]

Input

APB bridge

APB write data bus.

PRDATA[31:0]

Output

APB bridge

APB read data bus.


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