A.2. On-chip signals

Table A.2 shows the non-AMBA signals of the RTC.

Table A.2. On-chip signals

NameTypeSource or destinationDescription

CLK1HZ

Input

Clock generator

1Hz clock input. This signal clocks the counter during normal operation.

nRTCRSTInputReset controllerRTC reset signal (active LOW). It can be asserted asynchronously, but must be deasserted synchronously to CLK1HZ.

nPOR

InputReset controllerRTC power-on reset signal for RTCMR and offset registers. These registers must retain their value over the bus reset signal PRESETn.

RTCINTR

Output

Interrupt controller

Interrupt signal to the interrupt controller. When HIGH, this signal indicates that a valid match has occurred between the counter value and the Match Register.

SCANENABLE

Input

Test controller

Placeholder for scan enable input signal.

SCANINPCLK

Input

Test controller

Placeholder for scan data input signal (PCLK domain).

SCANOUTPCLK

Input

Test controller

Placeholder for scan data output signal (PCLK domain).

SCANINCLK1HZ

Input

Test controller

Placeholder for scan data input signal (CLK1HZ domain).

SCANOUTCLK1HZ

Input

Test controller

Placeholder for scan data output signal (CLK1HZ domain).


Copyright © 2001, 2017 ARM Limited or its affiliates. All rights reserved.ARM DDI 0224C
Non-ConfidentialID052317