2.3.1. Interface reset

The RTC requires three reset signals to reset the various parts, nRTCRST, nPOR, and PRESETn. PRESETn must be asserted LOW for a period long enough to reset the slowest block in the on-chip system, and then be taken HIGH again. The RTC requires PRESETn to be asserted LOW for at least one PCLK period. PRESETn is used to reset most of the logic that is clocked by PCLK.

The interrupt output RTCINTR is LOW after reset.

Power on Reset (nPOR) resets the Match Register and offset register, and must therefore be deasserted synchronously to PCLK.

nRTCRST is used to reset the logic in the CLK1HZ domain, and must therefore be deasserted synchronously to CLK1HZ. In addition, nRTCRST must only be generated as a result of nPOR, and not a soft reset. Failure to do this results in the loss of the RTC value. PRESETn can be generated as a result of either nPOR or a soft reset.

The values of registers after reset are defined in Chapter 3 Programmers model.

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