2.3.3. RTC operation

After reset, values must be written to the Load Register, RTCLR, and Match Register, RTCMR.

The counter increments by 1 on the rising edge of CLK1HZ.

To enable the interrupt, set the RTCIMSC register by writing a 1.

When the counter and match registers are identical, and the interrupt is not masked, the RTCINTR interrupt is asserted HIGH. The interrupt is cleared by writing 1 to the Interrupt Clear Register, RTCICR.

By using a 1Hz clock signal for CLK1HZ, the counter increments in one second intervals. This can be used to implement a real-time clock function in software and a basic alarm time function.

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