2.1. Real Time Clock overview

The RTC comprises:

An external processor can use the AMBA APB interface to read and write data to the RTC, and access its control and status information.

The 32-bit counter is incremented on successive rising edges of the input clock CLK1HZ. Counting in one second intervals is achieved by using a 1Hz clock signal for CLK1HZ. The counter is free-running and cannot be loaded. On reset, the counter:

RTC is loaded or updated by writing to the Load Register, RTCLR.

Reading the Data Register, RTCDR, gives the current value of the RTC.

The Match Register is programmed by writing to RTCMR. The counter and match values are compared in a comparator. When both values are equal, the RTCINTR interrupt is asserted HIGH. An external processor can use the interrupt to implement a basic time alarm function. The interrupt is cleared by writing any data value to the Interrupt Clear Register, RTCICR. The value in the Match Register can be read at any time.

The RTCINTR interrupt can be masked by writing to the interrupt match set or clear register, RTCIMSC. The raw status of the interrupt can be obtained by reading the RTCRIS register, and the masked version can be read from the RTCMIS register.

Synchronization logic is implemented to prevent propagation of metastable values when reading RTCDR. This ensures the stability of the data, even at the point that the counter is incrementing.

Figure 2.1 shows an AMBA APB write access.

Figure 2.1. AMBA APB write access

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Figure 2.2 shows an AMBA APB read access.

Figure 2.2. AMBA APB read access

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Figure 2.3 shows the interrupt generation when the current RTC value (RTCDR) equals the Match Register value.

Figure 2.3. Interrupt generation

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