3.3.4. Control Register, RTCCR

RTCCR is a 1-bit control register. When bit[0] == 1, the counter enable signal is asserted to enable the counter. Table 3.5 shows the bit assignments for the RTCCR register.

Table 3.5. RTCCR register

Bits

Name

Type

Function

[31:1]

-

-

Reserved. Read unpredictable. Must be written as 0.

[0]

RTC start

RW

If set to 1, the RTC is enabled. After the RTC is enabled, do not write to this bit otherwise the current RTC value is reset to zero.

A read returns the status of the RTC.


Copyright © 2001, 2017 ARM Limited or its affiliates. All rights reserved.ARM DDI 0224C
Non-ConfidentialID052317