2.3. Reference peripherals

Figure 2.1 shows how the reference peripherals are interconnected within the Reference Peripherals Specification (RPS) block, and how they are connected to the bridge.

Figure 2.1. Block diagram of the RPS block and bridge

The base addresses of each of the peripherals (timer, interrupt controller, and remap and pause controller) are defined in the AHB to APB bridge interface, which selects the peripheral according to its base address. The whole APB address range is also defined in the bridge.

These base addresses can be implementation-specific. The peripherals standard specifies only the register offsets (from an unspecified base address), register bit meaning, and minimum supported function.

Table 2.1 shows the three bases and their current addresses in the EASY microcontroller.

Table 2.1. Peripherals base addresses


EASY base


Interrupt controller

0x8000 0000


0x8400 0000

Remap and pause controller

0x8800 0000


When writing software or test patterns to run on the system, the absolute hex addresses must not be used within the code. Instead, define the base addresses in a header and then use the offset to this base address.

The APB data bus is split into two separate directions:

This simplifies driving the buses because turnaround time between the peripherals and bridge is avoided.

In the default system, because the bridge is the only master on the bus, PWDATA is driven continuously. PRDATA is a multiplexed connection of all peripheral PRDATA outputs on the bus, and is only driven when the slaves are selected by the bridge during APB read transfers.

It is possible to combine these two buses into a single bidirectional bus, but precautions must be taken to ensure that there is no bus clash between the bridge and the peripherals.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A