2.5. System test methodology

Each AHB slave, AHB master, and APB peripheral must be tested in complete isolation. This means that components must be designed with test veneers that enable non-bus signals to be controlled and observed.

When a component is tested, a special test bit is set. This test bit switches these multiplexed signals to test registers (accessible through the AHB or APB), which effectively isolates each component from the rest of the system.

Test vectors must be written to test the component in isolation, making as few assumptions about the rest of the system as possible.

Figure 2.2. Simple test veneer example

A good example of this approach is provided by the test veneer for the ARM processor, which is described in the AMBA ARM7TDMI Interface Data Sheet. This approach is also used to test the peripherals on the APB bus.

Under normal conditions, when the TIC is not in use, the current bus master performs transfers to and from any one of the following slaves:

However, when test mode is entered, and the TIC is the current master, the following slaves can be accessed:

Note

Bus masters can become slaves during test mode. The EBI cannot be tested using the TIC because of the way test access is provided to the AHB bus. The TIC is a state machine driven by the test request inputs (TESTREQA and TESTREQB). It also contains a register that enables it to read address information from the test bus (TESTBUS) and drive it onto the AHB address bus (HADDR). However, it cannot drive the test bus. Instead, it overrides the normal function of the EBI, forcing it to provide a 32-bit channel between HRDATA and TESTBUS, passing out read data during a read test vector. Therefore, in test mode, the EBI cannot function as a slave.

TESTBUS must be a 32-bit channel. In a system which only supports a 16-bit or 8-bit external data bus, additional external pins such as address lines must be forced into a special test mode to supply the full 32-bit bidirectional channel required.

For more information about:

Note

The TESTREQA, TESTREQB and TESTBUS signals are the same as the TREQA, TREQB, and TBUS signals described in the AMBA Specification (Rev 2.0).

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential