2.2.2. Arbiter

The arbiter provides arbitration between bus masters competing for access to the AHB. Although there are only two bus masters in the EASY microcontroller, the ARM and the TIC, the arbiter has provision for up to four masters. To extend the number of masters, see Chapter 7 Designer’s Guide. The arbitration is currently assigned with a simple priority system, with the TIC as the highest priority, and the processor as the lowest (also the reset default). The arbitration scheme is not defined in the AMBA Specification and can be dependent on implementation.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A