4.10. Test interface controller

The Test Interface Controller (TIC) is a state machine that provides an AMBA AHB bus master for system test. It reads test write and address data from the external data bus TESTBUS (XD), and uses the External Bus Interface (EBI) to drive the external bus with test read data, allowing the use of only one set of output tristate buffers onto TESTBUS.

The TIC is used to convert externally applied test vectors into internal transfers on the AHB bus. A three-wire external handshake protocol is used, with two inputs controlling the type of vector that is applied and a single output that indicates when the next vector can be applied.

Typically the TIC is the highest priority AMBA bus master, which ensures test access under all conditions.

The TIC model supports address incrementing and control vectors. This means that the address for burst transfers can automatically be generated by the TIC.

Figure 4.38 shows the TIC module interface diagram.

Figure 4.38. TIC module interface diagram

Figure 4.38 represents a TIC module in a system where the external data bus becomes the test bus when performing test mode accesses. 16-bit and 8-bit data bus systems require, for example, 16 or 24 address lines to be reconfigured as bidirectional test port signals for the test mode access.

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