4.1.1. Signal descriptions

The APB bridge module signals are described in Table 4.1Figure 4.1.

Table 4.1. Signal descriptions for bridge module

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HADDR[31:0]

Address bus

Input

The 32-bit system address bus.

HTRANS[1:0]

Transfer type

Input

This indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HWRITE

Transfer direction

Input

When HIGH this signal indicates a write transfer, and when LOW, a read transfer.

HWDATA[31:0]

Write data bus

Input

The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended. However, this can easily be extended to allow for higher bandwidth operation.

HSELAPBif

Slave select

Input

Each APB slave has its own slave select signal, and this signal indicates that the current transfer is intended for the selected slave. This signal is a combinatorial decode of the address bus.

HRDATA[31:0]

Read data bus

Output

The read data bus is used to transfer data from bus slaves to the bus master during read operations. A minimum data bus width of 32 bits is recommended. However, this can easily be extended to allow for higher bandwidth operation.

HREADYin

HREADYout

Transfer done

Input/ output

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESP[1:0]

Transfer response

Output

The transfer response provides additional information on the status of a transfer. This module always generates the OKAY response.

PRDATA[31:0]

Peripheral read data bus

Input

The peripheral read data bus is driven by the selected peripheral bus slave during read cycles (when PWRITE is LOW).

PWDATA[31:0]

Peripheral write data bus

Output

The peripheral write data bus is continuously driven by this module, changing during write cycles (when PWRITE is HIGH).

PENABLE

Peripheral enable

Output

This enable signal is used to time all accesses on the peripheral bus. PENABLE goes HIGH on the second clock rising edge of the transfer, and LOW on the third (last) rising clock edge of the transfer.

PSELx

Peripheral slave select

Output

There is one of these signals for each APB peripheral present in the system. The signal indicates that the slave device is selected, and that a data transfer is required. It has the same timing as the peripheral address bus. It becomes HIGH at the same time as PADDR, but is set LOW at the end of the transfer.

PADDR[31:0]

Peripheral address bus

Output

This is the APB address bus, which can be up to 32 bits wide and is used by individual peripherals for decoding register accesses to that peripheral. The address becomes valid after the first rising edge of the clock at the start of the transfer. If there is a following APB transfer, the address changes to the new value, otherwise it holds its current value until the start of the next APB transfer.

PWRITE

Peripheral transfer direction

Output

This signal indicates a write to a peripheral when HIGH, and a read from a peripheral when LOW.

It has the same timing as the peripheral address bus.

Timing diagrams showing the relationship between AHB and APB transfers can be found in the APB Specification.

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