4.1.3.  Function and operation of module

The APB bridge responds to transaction requests from the currently granted AHB master. The AHB transactions are then converted into APB transactions. The state machine, shown in Figure 4.3, controls:

The individual PSELx signals are decoded from HADDR, using the state machine to enable the outputs while the APB transaction is being performed.

If an undefined location is accessed, operation of the system continues as normal, but no peripherals are selected.

Figure 4.3. State machine for AHB to APB interface

The individual states of the state machine operation are described in the following sections:

ST_IDLE

During this state the APB buses and PWRITE are driven with the last values they had, and PSEL and PENABLE lines are driven LOW.

The ST_IDLE state is entered from:

  • reset, when the system is initialized

  • ST_RENABLE, ST_WENABLE, or ST_IDLE, when there are no peripheral transfers to perform.

The next state is:

  • ST_READ, for a read transfer, when the AHB contains a valid APB read transfer

  • ST_WWAIT, for a write transfer, when the AHB contains a valid APB write transfer.

ST_READ

During this state the address is decoded and driven onto PADDR, the relevant PSEL line is driven HIGH, and PWRITE is driven LOW. A wait state is always inserted to ensure that the data phase of the current AHB transfer does not complete until the APB read data has been driven onto HRDATA.

The ST_READ state is entered from ST_IDLE, ST_RENABLE, ST_WENABLE, or ST_WENABLEP during a valid read transfer.

The next state is always ST_RENABLE.

ST_WWAIT

This state is needed because of the pipelined structure of AHB transfers, to allow the AHB side of the write transfer to complete so that the write data becomes available on HWDATA. The APB write transfer is then started in the next clock cycle.

The ST_WWAIT state is entered from ST_IDLE, ST_RENABLE, or ST_WENABLE, during a valid write transfer.

The next state is always ST_WRITE.

ST_WRITE

During this state the address is decoded and driven onto PADDR, the relevant PSEL line is driven HIGH, and PWRITE is driven HIGH.

A wait state is not inserted, because a single write transfer can complete without affecting the AHB.

The ST_WRITE state is entered from:

  • ST_WWAIT, when there are no more peripheral transfers to perform

  • ST_WENABLEP, when the currently pending peripheral transfer is a write, and there are no more transfers to perform.

The next state is:

  • ST_WENABLE, when there are no more peripheral transfers to perform

  • ST_WENABLEP, when there is one more peripheral write transfer to perform.

ST_WRITEP

During this state the address is decoded and driven onto PADDR, the relevant PSEL line is driven HIGH, and PWRITE is driven HIGH. A wait state is always inserted, because there must only ever be one pending transfer between the currently performed APB transfer and the currently driven AHB transfer. See the write transfer timing diagrams in the AMBA Specification (Rev 2.0) for more details.

The ST_WRITEP state is entered from:

  • ST_WWAIT, when there is a further peripheral transfer to perform.

  • ST_WENABLEP, when the currently pending peripheral transfer is a write, and there is a further transfer to perform.

The next state is always ST_WENABLEP.

ST_RENABLE

During this state the PENABLE output is driven HIGH, enabling the current APB transfer. All other APB outputs remain the same as the previous cycle.

The ST_RENABLE state is always entered from ST_READ.

The next state is:

  • ST_READ, when there is a further peripheral read transfer to perform

  • ST_WWAIT, when there is a further peripheral write transfer to perform

  • ST_IDLE, when there are no more peripheral transfers to perform.

ST_WENABLE

During this state the PENABLE output is driven HIGH, enabling the current APB transfer. All other APB outputs remain the same as the previous cycle.

The ST_WENABLE state is always entered from ST_WRITE.

The next state is:

  • ST_READ, when there is a further peripheral read transfer to perform

  • ST_WWAIT, when there is a further peripheral write transfer to perform

  • ST_IDLE, when there are no more peripheral transfers to perform.

ST_WENABLEP

A wait state is inserted if the pending transfer is a read because, when a read follows a write, an extra wait state must be inserted to allow the write transfer to complete on the APB before the read is started.

The ST_WENABLEP state is entered from:

  • ST_WRITE, when the currently driven AHB transfer is a peripheral transfer

  • ST_WRITEP, when there is a pending peripheral transfer following the current write.

The next state is:

  • ST_READ, when the pending transfer is a read

  • ST_WRITE, when the pending transfer is a write, and there are no more transfers to perform

  • ST_WRITEP, when the pending transfer is a write, and there is a further transfer to perform.

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