4.1.4. System description

This section describes how the HDL code for the APB bridge is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This should be read in conjunction with the HDL code.

Figure 4.4 shows the APB bridge module block diagram.

Figure 4.4. APB bridge module block diagram

The AHB to APB bridge comprises a state machine, which is used to control the generation of the APB and AHB output signals, and the address decoding logic which is used to generate the APB peripheral select lines.

All registers used in the system are clocked from the rising edge of the system clock HCLK, and use the asynchronous reset HRESETn.

Figure 4.5 shows the APB bridge HDL file.

Figure 4.5. APB bridge module system diagram

The main sections in this module are explained in the following paragraphs:

Constant definitions

The constant PADDRWIDTH sets the width of the peripheral address bus that is used, up to a maximum of 32 bits. This size depends on the size of address that is needed by the peripherals in the system. The default value is a 16-bit address bus.

The next two constants define the state machine states, and the top four address bits that are used to decode the peripheral select outputs. If the peripheral address map is changed from the default, these constants must be modified to match the changes.

AHB slave bus interface

This module uses the standard AHB slave bus interface, which comprises:

  • the valid transfer detection logic which is used to determine when a valid transfer is accessing the slave

  • the address and control registers, which are used to store the information from the address phase of the transfer for use in the data phase.

Because of the different AHB to APB timing of read and write transfers, either the current or the previous address input value is needed to correctly generate the APB transfer. A multiplexor is therefore used to select between the current address input or the registered address, for read and write transfers respectively.

APB transfer state machine

The transfer state machine is used to control the application of APB transfers based on the AHB inputs. The state diagram in Figure 4.3 shows the operation of the state machine, which is controlled by its current state and the AHB slave interface signals.

APB output signal generation

The generation of all APB output signals is based on the status of the transfer state machine:

  • PWDATA is a registered version of the HWDATA input, which is only enabled during a write transfer. Because the bridge is the only bus master on the APB, it can drive PWDATA continuously.

  • PENABLE is only set HIGH during one of three enable states, in the last cycle of an APB transfer. A register is used to generate this output from the next state of the transfer state machine.

  • The PSELx outputs are decoded from the current transfer address. They are only valid during the read, write and enable states, and are all driven LOW at all other times so that no peripherals are selected when no transfers are being performed.

  • PADDR is a registered version of the currently selected address input (HADDR or the address register) and only changes when the read and write states are entered at the start of the APB transfer.

  • PWRITE is set HIGH during a write transfer, and only changes when a new APB transfer is started. A register is used to generate this output from the next state of the transfer state machine.

  • The APBen signal is used as an enable on the PSEL, PWRITE and PADDR output registers, ensuring that these signals only change when a new APB transfer is started, when the next state is ST_READ, ST_WRITE, or ST_WRITEP.

AHB output signal generation

A standard AHB slave interface consists of the following three outputs:

  • HRDATA is directly driven with the current value of PRDATA. APB slaves only drive read data during the enable phase of the APB transfer, with PRDATA set LOW at all other times, so bus clash is avoided on HRDATA (assuming OR bus connections for both the AHB and APB read data buses).

  • HREADYout is driven with a registered signal to improve the output timing. Wait states are inserted by the APB bridge during the ST_READ and ST_WRITEP states, and during the ST_WENABLEP state when the next transfer to be performed is a read.

  • HRESP is continuously held LOW, because the APB bridge does not generate SPLIT, RETRY or ERROR responses.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A