4.2.3. Operation

The basic operation of the arbiter is to sample the HBUSREQ inputs from each of the masters in the system and determine which is currently the highest priority master requesting the bus. The output of the priority logic is a 4-bit encoding, which represents the master number of the highest priority master requesting the bus.

If no other master is actively using the bus, the output of the priority logic is decoded and used to generate the HGRANT outputs. The HGRANT outputs indicate which master drives the address and control signals after the current transfer has completed, as indicated by HREADY being HIGH.

The usual process for determining which master is granted is to use the output from the priority logic. However, under the following circumstances the arbiter keeps the current bus master granted irrespective of the HBUSREQ inputs:

Figure 4.8 shows the generation of the HGRANT and HMASTER signals.

Figure 4.8. HGRANT and HMASTER generation

The following signals are used in the arbiter:

GrantMaster

Indicates the number of the master whose HGRANT signal is currently asserted.

AddrMaster

Gives the number of the master that is currently driving the address/control signals. This is the same as the HMASTER output.

DataMaster

Gives the number of the master that currently owns the data bus and is either driving the write data bus or is reading from the read data bus.

The relationship between these signals is shown in Figure 4.9. This diagram represents the pipelined nature of the bus, and shows how the pipeline is advanced when the HREADY signal is HIGH.

Figure 4.9. Signal relationships

Arbitration priority scheme

The arbiter is supplied with a fixed priority scheme:

  • HBUSREQ(3) is the highest priority.

  • HBUSREQ(0) is the second highest priority. This must only be connected to a Pause input.

  • HBUSREQ(2) is the middle priority.

  • HBUSREQ(1) is the lowest priority and default bus master. This is usually used for an uncached ARM core.

Bus master 0 is reserved for the dummy bus master, which never performs real transfers. This master is granted either when the Pause input is asserted, or when the current master is performing a locked transfer which has received a split response.

If required, this priority scheme can be updated by changing the logic which takes the masked version of the HBUSREQ signals, called Request, and generates the 4-bit encoded master number, called TopRequest.

Locked operation

The arbiter also has to deal with locked operations. A bus master is considered to have locked access to the bus if the master has its HLOCK signal asserted to the arbiter at the point when it is granted access. The master must then remain the only granted master until its HLOCK signal is deasserted.

The logic required to implement locked operation is added to Figure 4.10. A single output, called HMASTLOCK, is used to indicate when a master has locked access to the bus. This output is generated by selecting the appropriate HLOCK input, depending on which master is granted the bus in the next cycle.

Figure 4.10. Locked transfers

The HMASTLOCK output is then used within the arbiter to force the next granted master to be the same as the currently granted master, effectively locking the master on the bus. The master then remains granted until it deasserts the lock.

Split responses

The arbiter performs a special function for transfers which receive a SPLIT response. The arbiter must ensure that the master which received the SPLIT response is not granted again until the slave has indicated that it is ready to complete the transfer (using the HSPLITx signals). To implement the split response function, the arbiter requires a mask register with one bit in the register for each bus master in the system.

Whenever a master receives a SPLIT response, the appropriate bit in the SplitMask register is set and, when the slave indicates that the particular master is able to complete, the appropriate bit in the SplitMask register is cleared. Figure 4.11 shows the split logic.

Figure 4.11. Split logic

On the input to the arbiter, the SplitMask register is used to mask out any incoming request signals from masters which have received a SPLIT response.

The required operation of the arbiter when a locked bus master receives a SPLIT response is to grant a dummy bus master (which only performs IDLE transfers) until the master is unsplit and can return to the bus to complete the locked transfer. A dedicated section of the arbiter is used to detect a SPLIT response on a locked bus master. This forces the HGRANT and HMASTER outputs to grant the dummy bus master until the master is unsplit.

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