4.3.1. Signal description

Table 4.3 shows the signal descriptions for the decoder module

Table 4.3. Decoder module signal descriptions

Signal

Type

Direction

Description

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HADDR[31:0]

Address bus

Input

The 32-bit system address bus.

Remap

Reset memory map

Input

When LOW, the internal memory is not part of the system memory map, and external memory is mapped from address 0x00000000 which normally contains the system startup code. In normal operation this signal is HIGH, allowing use of the internal memory.

HSELx

Slave select

Output

Slave select to each system bus slave.

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