4.3.4. System description

The following paragraphs give a description of how the HDL code for the decoder is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the inputs, and outputs used in the module. This part should be read together with the HDL code. Figure 4.14 shows the decoder module block diagram.

Figure 4.14. Decoder module block diagram

The decoder comprises a simple block of combinational logic, which is used to decode the address and system remap inputs to directly generate the slave select outputs. Figure 4.15 shows the decoder HDL file.

Figure 4.15. Decoder module system diagram

The whole of the decode logic is contained in one if statement. During reset, the default slave is selected, and at all other times, the HADDR and Remap inputs are decoded and used to generate the HSELx outputs.

The minimum number of address bits needed to select a slave are used, keeping the combinational logic as small as possible.

This section of code is used to define the memory map for the whole system. If modules are added, removed, or moved to new locations, the code must be modified to match these system changes, ensuring that the correct slave is selected for each address used.

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