4.4.1. Signal descriptions

Table 4.4 shows the signal descriptions for the default slave module

Table 4.4. Default slave module signal descriptions

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HTRANS[1:0]

Transfer type

Input

Indicated the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HSEL

Default slave select

Input

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

HREADYout

Transfer done

Output

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal is only driven LOW to generate a two cycle error response.

HRESP[1:0]

Transfer response

Output

The transfer response provides additional information on the status of a transfer. This module only generates the OKAY and ERROR responses.

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