4.4.3. System description

This section describes how the HDL code for the default slave is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This should be read together with the HDL code.

Figure 4.17 shows the default slave module block diagram.

Figure 4.17. Default slave module block diagram

The default slave comprises the invalid transfer detection logic and two simple sets of combinational logic and registers, which are used to generate the HREADY and HRESP outputs.

Figure 4.18 shows the decoder HDL file.

Figure 4.18. Default slave module system diagram

The internal signal Invalid is set HIGH during the final cycle of the address phase of an invalid transfer (when HREADYin is set HIGH, a NONSEQUENTIAL or SEQUENTIAL transfer is performed, and the default slave is selected), and is set LOW at all other times.

This signal is then passed to the response generation logic, which is split into two sections for the HREADYout and HRESP outputs. This logic generates the response values for the output registers. HREADYout is set LOW during the first cycle of the data phase, as is required for the two cycle ERROR response, and HRESP is set to ERROR for the two-cycles of the data phase.

At all other times, the default slave generates a zero wait OKAY response.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential