4.5.1. Signal descriptions

Table 4.5 lists signal descriptions for the master to slave multiplexor module

Table 4.5. Master to slave multiplexor signal descriptions

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HMASTER[3:0]

Master number

Input

These signals from the arbiter indicate which bus master is currently performing a transfer, and is used by slaves which support split transfers to determine which master is attempting an access.

HREADY

Transfer done

Input

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HADDRx[31:0]

HADDR[31:0]

Address bus

Input/ output

The 32-bit system address bus.

HTRANSx[1:0]

HTRANS[1:0]

Transfer type

Input/ output

These signals indicate the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HWRITEx

HWRITE

Transfer direction

Input/ output

When HIGH this signal indicates a write transfer, and when LOW, a read transfer.

HSIZEx[2:0]

HSIZE[2:0]

Transfer size

Input/ output

These signals indicate the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The protocol allows for larger transfer sizes up to a maximum of 1024 bits.

HBURSTx[2:0]

HBURST[2:0]

Burst type

Input/ output

These signals indicate if the transfer forms part of a burst. Both four beat and eight beat bursts are supported and the burst can be either incrementing or wrapping.

HPROTx[3:0]

HPROT[3:0]

Protection control

Input/ output

The protection control signals provide additional information about a bus access and are primarily intended for use by any module that wishes to implement some level of protection.

HWDATAx[31:0]

HWDATA[31:0]

Write data bus

Input/ output

The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended, however this can easily be extended to allow for higher bandwidth operation.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential