4.5.3. System description

This section describes how the HDL code for the master to slave multiplexor is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This should be read together with the HDL code.

Figure 4.20 shows the master to slave module block diagram.

Figure 4.20. Master to slave multiplexor module block diagram

Master to slave multiplexor module block diagram

The master to slave multiplexor module comprises a set of multiplexors for each address, control and data output from the system bus masters. A set of registers is also used to hold the previous value of the HMASTER input.

Figure 4.21 shows the master to slave multiplexor HDL file.

Figure 4.21. Master to slave multiplexor module system diagram

Master to slave multiplexor module system diagram

The multiplexor for each master signal has an input for each system bus master, and a ground connection for the default master signal values. The master number is decoded, and used to select the correct input signal.

The multiplexors are constructed using case statements, ensuring that there is no priority to the master selection logic.

An HREADY enabled register is used to hold the previous value of HMASTER, because the HWDATA master outputs are always running one cycle behind the other address and control signals, because of the pipelined bus. The enable is used to ensure that the value is only updated when the previous transfer has completed.

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