4.6.1. Signal descriptions

Table 4.6 shows the signal descriptions for the slave to master multiplexor module.

Table 4.6. Slave to master multiplexor signal descriptions

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HSELx

Slave select

Input

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave.

HRDATAx[31:0]

HRDATA[31:0]

Read data bus

Input/ output

The read data bus is used to transfer data from bus slaves to the bus master during read operations.

HREADYx

HREADY

Transfer done

Input/ output

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESPx[1:0]

HRESP[1:0]

Transfer response

Input/ output

The transfer response provides additional information on the status of a transfer.

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