4.6.3. System description

This section describes how the HDL code for the slave to master multiplexor is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This part should be read together with the HDL code.

Figure 4.23 shows the slave to master module block diagram.

Figure 4.23. Slave to master multiplexor module block diagram

Slave to master multiplexor module block diagram

The slave to master multiplexor module comprises a set of registers to store the previous slave select values, and a set of multiplexors for the read data and slave response signals.

Figure 4.24 shows the slave to master multiplexor HDL file.

Figure 4.24. Slave to master multiplexor module system diagram

Slave to master multiplexor module system diagram

To allow the use of case statements for the multiplexors, the HSEL slave select inputs are combined to create a multi-bit bus signal. This bus is then registered, and used as the select control on the three multiplexors, one each for the read data and two response signals. The select register is enabled with the internal HREADY signal, ensuring that the outputs only change when the previous transfer has finished.

Because the default slave does not generate any read data, one input to the HRDATA multiplexor is tied LOW, so that when the default slave is selected, no read data appears on HRDATA.

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