4.7.1. Signal descriptions

Table 4.7 shows the signal descriptions for the reset controller.

Table 4.7. Reset controller signal descriptions

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

POReset

Power-on reset

Input

Power-on reset input. This active LOW signal causes a cold reset when LOW. Can be asserted asynchronously to HCLK.

HRESETn

Reset

Output

The bus reset signal is active LOW, and is used to reset the system and the bus.

The source of the POReset signal is implementation-dependent.

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