4.7.2. Function and operation of module

HRESETn is asserted LOW, and is used to indicate a reset condition where all bus and system states must be initialized. This signal is suitable as an asynchronous clear into state machine flip-flops, and for resetting any peripheral registers that require initialization.

During reset, the arbiter grants the bus to the default reset bus master, and the decoder selects the default slave.

Assertion (the falling edge) of HRESETn is asynchronous to HCLK. De-assertion (the rising edge) of HRESETn is synchronous to the rising edge of HCLK. HRESETn is only asserted during a power-on reset condition, caused by the assertion of the POReset signal. The POReset input is an asynchronous input, so a synchronizing register is required to eliminate propagation of metastable values. Figure 4.26 shows the operation of the HRESETn signal with respect to an example POReset input signal and the system clock.

Figure 4.26. Reset signal timing

The reset controller contains a state machine running from the rising edge of HCLK. The HRESETn signal directly reflects a single bit of the current state, minimizing the combinational logic applied to the reset output.

Figure 4.27 shows the state machine for the reset controller.

Figure 4.27. State machine for reset controller

The four states are described in:

ST_POR

During this state, the system is initialized when the reset line is asserted. This state must be preserved by a power on reset cell or controller, until the system bus clock is running and stable, and the system power supply has reached its correct operating voltage (within its allowed limits).

The ST_POR state is entered from:

  • reset, when the external reset input is first asserted LOW

  • ST_POR when the external reset input is still asserted and the system clock is running.

The next state is:

  • ST_INI1 when the external reset input is deasserted

  • ST_POR when the external reset input is still asserted and the system clock is running.

If there is a clock valid signal in the system, this must be used to prevent the ST_POR state from being exited until the clock is valid.

ST_INI1

This state is used to hold the HRESETn output LOW for an extra cycle after the external reset is deasserted.

This state is always entered from ST_POR on the first rising edge of the clock that the external reset is HIGH.

The next state is always ST_INI2.

ST_INI2

This state is used in the same way as ST_INI1.

This state is always entered from ST_INI1.

The next state is always ST_RUN.

ST_RUN

This state is used during normal system operation when the HRESETn output is set HIGH.

This state is held until the external reset is re-asserted.

The default reset controller implementation asserts HRESETn for two cycles after the external reset is deasserted, but this can be altered by adding extra ST_INI states to the state machine, so that it takes more cycles to reach the final ST_RUN state.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential