4.7.3. System description

The following paragraphs give a description of how the HDL code for the reset controller is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This part should be read together with the HDL code.

Figure 4.28 shows the reset controller module block diagram.

Figure 4.28. Reset controller module block diagram

The reset controller is comprised of a register used to synchronize the external reset input, and a state machine used to control the generation of the system reset output.

All registers used in the system are clocked from the rising edge of the system clock HCLK.

Figure 4.29 shows the reset controller HDL file.

Figure 4.29. Reset controller module system diagram

The main sections in this module are explained in the following paragraphs:

Asynchronous reset input synchronization

The asynchronous external reset is first passed through a rising-edge-triggered register. This is to avoid metastability, because of the arrival time of the input relative to the system clock when used in the state machine.

Reset state machine

The state machine shown in Figure 4.27 is used to control the generation of the system reset output, based on the status of the synchronized external reset input and the system clock.

The number of cycles the module holds HRESETn asserted after the de-assertion of the external reset can be changed by altering the number of initialization states between the first and last states.

Reset output generation

The reset output is generated directly from bit 0 of the state machine registers, gated with the external reset input. This allows asynchronous assertion of the reset output when the external reset input is set LOW and the system clock is not running, but ensures that de-assertion is synchronous to the rising edge of the clock.

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